This invention relates to the packaging of electronic components and, more particularly, to an improved very large hybrid module having high density and high performance characteristics.
In recent years, there have been rapid advances in the development of very large scale and very high speed integrated circuits. This has led to integrated circuit chips of ever increasing sizes, which has been accompanied by a dramatic increase in the required number of input/output leads to the chips. At the same time, the increased functional density has resulted in a corresponding increase in power dissipation requirements. While these developments are generally desirable, problems arise because conventional single chip packaging techniques do not offer interconnection systems compatible with high speed operation nor do they offer a heat removal mechanism which is required for the high power densities achieved by these new integrated circuit chips. At the present time, integrated circuit chips are typically packaged in individual cases which in turn are mounted to, and interconnected via, printed circuit boards. The increases in the functional capability and the input/output count of these chips continues to enlarge the chip package and the required packaging real estate. Typically, a two inch square is needed for a 256 input/output pin grid array.
As the size of integrated circuit chip packages increases, the distance between the chips lengthens, the complexity of the printed circuit board rises, and high speed operation deteriorates. The larger packages also have cumbersome thermal interfaces with high impedance thermal paths.
To overcome interconnection length problems, the semiconductor industry has developed large multi-chip packages which employ thick or thin film interconnect technology, thereby eliminating individual chip packages. As a means of further improving interconnections and bringing the chips into closer proximity, the chips are often mounted on a multi-layer fine line polyimide dielectric. Thus, packages as large as four inches square and containing in excess of 100 chips in a single hermetic enclosure have been developed.
Although the individual chips are tested prior to mounting on the dielectric, testing is difficult once the chips are bonded to the dielectric. Probing a field cluttered with wire bonds or TAB connections can lead to subtle and not readily detectable damage, possibly initiating a long term failure mechanism. After the lid of the hermetic enclosure is sealed, the removal of the lid, or impervious coatings, for repair purposes and subsequent resealing pose significant problems.
A further problem with the aforedescribed arrangement is that when chips are mounted on an organic dielectric substrate, additional thermal impedance is introduced and there is a potential outgassing and ionic contamination problem from the dielectric substrate within the hermetic enclosure.
An alternative to multi-chip packaging is wafer scale integration wherein a two to four inch diameter wafer is mounted within a hermetic enclosure or under an impervious overcoat. This approach goes a long way toward minimizing lead length, but results in poor yields, testability problems and high "up front" cost.
Another recently developed packaging technique which aspires to provide hermetically equivalent environmental protection by using a topical passivation or overcoat results in weight savings and size advantages. However, cleanliness and ionic or moisture penetration represent formidable challenges.
It is therefore a primary object of this invention to provide a cost effective chip package which resolves all of the aforedescribed outstanding problems while conforming to established industry standards for overall size and shape.
A more specific object of this invention is to provide an integrated circuit chip module capable of interconnecting a multitude of high speed devices, each having as many as several hundred input/output connections.
A further object of this invention is to provide such a module with an appropriate heat removal mechanism.
Yet another object of this invention is to provide such a module with dense hermetic packaging of a number of integrated circuit chips.
It is still a further object of this invention to provide such a module wherein the interconnection system facilitates reliable chip to chip communication at greater than a 100 megahertz rate within a limited area, with localized sections being able to accommodate higher frequency circuitry utilizing GaAs chips operating at gigahertz rates.
It is yet another object of this invention to provide such a module where the interconnection medium does not introduce detrimental outgassing into the hermetic enclosure.
Still a further object of this invention is to provide a module which permits electrical signal access to every one of the chip input/output pads from the outside of the hermetic enclosure for rapid in-circuit electrical testing after sealing of the hermetic enclosure, with the hermetic enclosure design being able to accommodate a reasonable number of unseal/seal cycles. Further, it is desired to have the capability of external cut and jumper reworkability of the package.